Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).
Early MOSFET processes used one type of doping to create either positive or negative channel transistors. More recent designs, referred to as complementary metal oxide semiconductor (CMOS) devices, use both positive and negative channel devices in complementary configurations. While this requires more manufacturing steps and more transistors, CMOS devices are advantageous because they utilize less power, and the devices may be made smaller and faster.
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide as a gate dielectric material becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric material of MOSFET devices. The term “high k material” as used herein refers to a dielectric material having a dielectric constant of about 4.0 or greater. If high k materials are successfully implemented in transistor designs, the effective oxide thickness of the gate dielectric is expected to be reduced, increasing device performance.
However, using high k dielectric materials as a gate dielectric of transistors can present problems. Some high k dielectric materials have been found to pin the work function of a transistor to undesirable levels. The work function of the transistor affects the threshold voltage. For example, in CMOS devices, it is desirable to achieve a symmetric threshold voltage Vt for the PMOS transistor and the NMOS transistor. If high k dielectric materials are used for the gate dielectric, a symmetric threshold voltage Vt may not be achievable.
U.S. patent application Ser. No. 11/187,197 filed on Jul. 21, 2005, entitled, “CMOS Transistors With Dual High-k Gate Dielectric and Methods of Manufacture Thereof,” and U.S. patent application Ser. No. 10/870,616, filed on Jun. 17, 2004, entitled, “CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof,” which applications are incorporated herein by reference, disclose CMOS devices having PMOS transistors and NMOS transistors with different high k gate dielectric materials used as a gate dielectric, to avoid problems with the pinning of the work function.
Another problem in the design and manufacture of transistor devices is that in advanced technologies, a reduced junction depth Xj and sheet resistance Rs are required. The thicker the junction depth Xj, the more the short channel effects such as hot carrier effects become severe and degrade transistor reliability, causing source and drain leakage and/or punch-through. If a transistor has a high sheet resistance Rs, then drive current and circuit speed are degraded, thus making the transistor less reliable for use in high-performance and/or high-speed applications.
U.S. Pat. No. 6,921,691 issued on Jul. 26, 2005 issued to Li, et al., which is hereby incorporated herein by reference, discloses forming recesses in a workpiece and filling the recesses with a dopant-bearing metal. An anneal process is used to form doped regions within the workpiece.
What are needed in the art are CMOS designs and fabrication methods wherein the effective gate dielectric thickness, the junction depth, and the sheet resistance are reduced, and wherein the threshold voltages for the PMOS and NMOS transistors are symmetric.